Fork of vcd with basic SystemVerilog support
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294 lines
2.0 KiB

$date
Fri Nov 21 16:56:29 2014
$end
$version
GHDL v0
$end
$timescale
1 fs
$end
$var reg 1 ! e_clk $end
$var reg 1 " e_rst $end
$var reg 1 # e_ren $end
$var reg 1 $ e_wen $end
$var reg 4 % e_d[3:0] $end
$var reg 4 & e_q[3:0] $end
$var reg 1 ' e_empty $end
$var reg 1 ( e_mid $end
$var reg 1 ) e_full $end
$scope module fifo1 $end
$var reg 1 * clk $end
$var reg 1 + rst $end
$var reg 1 , ren $end
$var reg 1 - wen $end
$var reg 4 . d[3:0] $end
$var reg 4 / q[3:0] $end
$var reg 1 0 empty $end
$var reg 1 1 mid $end
$var reg 1 2 full $end
$comment regs is not handled $end
$var reg 2 3 w_adr[1:0] $end
$var reg 2 4 r_adr[1:0] $end
$upscope $end
$enddefinitions $end
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