Fork of vcd with basic SystemVerilog support
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Sadoon AlBader 9601a9091c README.md makes more sense 2 months ago
.github/workflows Add CI 2 years ago
.gitignore fixed dumpvars,] & added .gitignore 1 year ago
LICENSE added myself to the copyright 2 months ago
Makefile better makefile install, added uninstall option 2 months ago
README.md README.md makes more sense 2 months ago
full_adder_tb.vcd Full fork, new sample 1 year ago
vcd.c fixed dumpvars,] & added .gitignore 1 year ago

README.md

VCD file command line viewer

Lightweight command line remplacement to GTKWave (16801 KB vs 6 KB)

Forked to support SystemVerilog.

Download

No binary releases available, compile it yourself :) Just type make.

Usage

Usage: vcd [OPTION]... [FILE]

 -h     : display this help screen
 -v=0   : verbose level (0:fatal,1:error,2:warning,3:debug)
 -w=2   : sample ascii width (1,2,...)
 -r=2   : rounded wave (0:none,1:pipe,2:slash)
 -c=32  : name column width
 -s=a,b : comma separated scopes to display

Examples

vcd sim_fifo.vcd
vcd  < in.vcd > out.txt

Preview

43 samples / Fri Nov 21 16:56:29 2014 / 1 fs
+-- fifo1
|        clk(*)[ 1]: ¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯  
|        rst(+)[ 1]: ___¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯  
|        ren(,)[ 1]: ¯¯¯¯¯____¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯__¯¯__________¯¯¯¯  
|        wen(-)[ 1]: ¯¯¯¯¯__¯¯¯¯________¯¯__¯¯__¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯  
|     d[3:0](.)[ 4]: ZZZZZ11ZZZZ22334455ZZ66ZZ77ZZZZZZZZZZZZZZZZ  
|     q[3:0](/)[ 4]: UUZZZZ0011ZZZZZZZZZZZZZZZZ33ZZ4455667700ZZZ  
|      empty(0)[ 1]: UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU  
|        mid(1)[ 1]: UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU  
|       full(2)[ 1]: UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU  
| w_adr[1:0](3)[ 2]: UU00001111112233001111222233333333333333333  
| r_adr[1:0](4)[ 2]: UU00000011111111111111222233330011223333333